(a) Field of the Invention
The present invention related to a variable capacitor used in an integrated circuit of a differential structure, and more particularly, to a variable capacitor capable of reducing an area required for an integrated circuit and reducing a production cost thereof.
(b) Description of the Related Art
In general, a structure in which two variable capacitors formed to be symmetrical to each other are connected with each other is employed in a high-frequency integrated circuit that is operated by using a differential structure.
FIG. 1 illustrates a structure of a voltage controlled oscillator (VCO) that is operated by using a differential structure. Among high-frequency integrated circuits each of which is operated by using the differential structure, the voltage controlled oscillator is one of the integrated circuits in which a variable capacitor is most frequently used. FIG. 1 shows a cross-coupled VCO, which includes an LC tank 11 for determining an oscillation frequency, a variable capacitor (e.g., a varactor) 12 for varying an oscillation frequency, and an amplification stage 13 for continuously oscillating an oscillator.
In general, an RF front-end is not operated on only one frequency, and has a specific operating frequency range and is required to vary operating frequencies according to a wireless communication environment. The operating frequencies may be varied by adjusting values of elements constituting an integrated circuit. For example, a capacitance value may be employed. In the case of FIG. 1, the varactor 12 which facilitates adjustment of C values as well as the LC tank 11 for determining the oscillation frequency are essentially used. The varactor 12 is mainly formed by using diodes or MOSFETs. For convenience of illustration, FIG. 1 illustrates the case of the diodes.
FIG. 2 illustrates a variable capacitor employing diodes shown in FIG. 1. As shown in FIG. 1, the variable capacitor 12 is connected between two differential signal lines formed in an integrated circuit of a differential structure, and employs two diodes 21n and 21p. Anodes of the two diodes 21n and 21p are connected with each other. A source voltage VDD is applied to cathode nodes 22n and 22p of the diodes 21n and 21p, and a control voltage Vctrl for controlling a parasitic capacitance component is applied to anode nodes thereof.
In general, the control voltage Vctrl is generated to be lower than the source voltage VDD. A lower voltage is applied to anode nodes of the two diodes than that of cathode nodes thereof, and resultantly a reverse bias is applied to both of the two diodes. Sizes of depletion regions formed in the two diodes are adjusted depending on a magnitude of the reverse bias, thereby varying a parasitic capacitance. Herein, virtual ground nodes are formed in the anode nodes at which the two diodes are connected. The cathode nodes 22n and 22p of the two diodes respectively serve as differential outputs (negative output and positive output) of VCO, which are connected with differential buffers.
FIG. 3 illustrates a case that the variable capacitor shown in FIG. 1 is formed by using MOSFETs. When the MOSETs are employed, both of NMOSs and PMOSs may be used. For convenience of description, a method employing the PMOSs will be described hereinafter. However, a variable capacitor formed by using a method employing the NMOSs is operated in a same method as the case of the method employing the PMOSs.
As shown in FIG. 3, two PMOSs 31n and 31p are employed. Sources S and drains D thereof are connected with each other, and connection points thereof serve as virtual ground nodes of an entire circuit. A control voltage Vctrl is applied to the virtual ground nodes to adjust a capacitance of the variable capacitor. A varactor is formed by using a same principle as the case of FIG. 2, in which a gate capacitance is varied depending on magnitudes of a source voltage VDD applied to a gate G and the control voltage Vctrl applied to the drain and the source of the corresponding PMOS in the two PMOSs 31n and 31p. 
FIG. 4 illustrates a concept of an actual layout of a variable capacitor formed by using diodes shown in FIG. 2. As shown in FIG. 4, in the two diodes 21n and 21p shown in FIG. 2, a plurality of PN junctions are laid out in a finger form. Herein, the finger form indicates a type of a semiconductor disposing method for improving an area efficiency on an integrated circuit by repeatedly using a plurality of PN junctions. For example, each of the diodes 21n and 21p shown in FIG. 4 may have 8 fingers.
When the circuit diagram shown in FIG. 2 corresponds to a semiconductor layout shown in FIG. 4, N regions of a first diode 21n formed of a plurality of PN junctions are connected with each other to form a node 22n, and P regions thereof are connected with each other to be connected with the control voltage Vctrl. Similarly, N regions of a second diode 21p are connected with each other to form a node 22p, and P regions thereof are connected with each other to be connected with the control voltage Vctrl.
FIG. 5 illustrates a concept of an actual layout of a variable capacitor formed by using PMOSs shown in FIG. 3. As shown in FIG. 5, in the PMOSs 31n and 31p shown in FIG. 3, a plurality of unit PMOSs are laid out in a finger form. In this case, the finger form indicates a type of a semiconductor disposing method for improving an area efficiency on an integrated circuit by repeatedly a plurality of unit PMOSs. For example, each of the PMOSs 31n and 31p shown in FIG. 5 may have 4 fingers.
When the circuit diagram shown in FIG. 3 corresponds to a semiconductor layout shown in FIG. 5, gates G of a first PMOS 31n are connected with each other to form a node 32n, and drains D and sources S are connected with each other to be connected with the control voltage Vctrl. Similarly, gates G of a second PMOS 31p are connected with each other to form a node 32p, and drains D and sources S are connected with each other to be connected with the control voltage Vctrl.
Although the case of forming the varactor by using the PMOSs has been described in the above description, the same layout and description are applied to a case of using NMOSs.
The variable capacitor formed as such is most frequently used in the VCO. In the case of the VCO, the variable capacitor plays an important role to generate carrier frequencies on a high-frequency system. An undesired resistance component exists in an internal circuit portion of the VCO causes noise generation, and phase noise which is one of main performance indexes of the VCO may be degraded.
Various factors which degrade the phase noise of the VCO exist, but one of the factors is a varactor. As described above, the varactor is essential to vary the operating frequencies of the VCO. However, as shown in FIG. 4 and FIG. 5, the varactor has more complex structure than that of a general MIM capacitor and uses a depletion region. Accordingly, the varactor has a relative low quality factor. Herein, the low quality factor indicates a large parasitic resistance component and a high power leakage. Accordingly, it is essential to minimize this parasitic resistance component in the varactor.
However, according to Related Art, a desired parasitic resistance component is generated in not only elements constituting a varactor by layout complexity on an integrated circuit and but also metal lines of interconnection lines which connect the diodes 21n and 21p and PMOSs 31n and 31p with each other as shown in FIG. 4 and FIG. 5.
Background techniques of the prevent invention are disclosed in Korea Patent No. 0645928 (published on Nov. 14, 2006)